A 2–4 GHz fast-locking frequency multiplying delay-locked loop

IEICE Electronics Express

Jongsun Kim¹  B-H Bae¹ 

[1] Electronic and Electrical Engineering, Hongik University

关键词: multiplying DLL;    MDLL;    frequency multiplier;    clock generator;    clock multiplier;    fast locking;    PLL;    DLL;   

DOI  :  10.1587/elex.13.20161056

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0–4.0 GHz with a programmable frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while consuming 6.7 mW at 2 GHz from a 1.2 V supply. Compared with the conventional architecture, the locking time has been reduced about 80%.

【 授权许可】

CC BY