Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm

The Journal of Engineering

Chitrakant Sahu¹  Jawar Singh¹ 

[1] Department of Electronics and Communication Engineering, PDPM Indian Institute of Information Technology, Design and Manufacturing Jabalpur, Madhya Pradesh, India

关键词: inverter circuit;    static r;    om access memory;    double gate junctionless transistors;    lower OFF state current;    steep subthreshold slope;    DG inversion-mode FETs;    SRAM cell stability;    coupled device-circuit methodology;    ATLAS TCAD mixed-mode simulator;    CMOS configuration;    complementary metal-oxide semiconductor configuration;    transient response;    pass gate logic;    drain-induced barrier lowering;    field effect transistors;   

DOI  :  10.1049/joe.2013.0269

学科分类：工程和技术（综合）

来源: IET

【 摘 要 】

The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V th for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD) mixed-mode simulator.

【 授权许可】

CC BY