Stage-dependent minimum bit resolution maps of full-parallel pipelined FFT/IFFT architectures incorporated in real-time optical orthogonal frequency division multiplexing transceivers

The Journal of Engineering

Jianming Tang¹  Kai Wang¹  Roger P. Giddings²  Wenyan Yuan²  Min Wang²  Junjie Zhang²  Bingyao Cao³ 

[1] Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai 200072, People'School of Electronic Engineering, Bangor University, Bangor LL571UT, UK;s Republic of China

关键词: field programmable gate array;    DSP complexity;    OOFDM transceivers;    analogue-to-digital converter/digital-to-analogue converter resolutions;    IEVM;    stage dependent minimum bit resolution maps;    fast Fourier transform;    digital signal processing;    full-parallel pipelined FFT/IFFT architectures;    DSP element;    FPGA logic resource;    real-time optical orthogonal frequency division multiplexing transceivers;    inverse error vector magnitude;    identified maps;    numerical explorations;   

DOI  :  10.1049/joe.2014.0181

学科分类：工程和技术（综合）

来源: IET

【 摘 要 】

Fast Fourier transform (FFT) and inverse FFT (IFFT) are the fundamental algorithms at the heart of optical orthogonal frequency division multiplexing (OOFDM) transceivers. The high digital signal processing (DSP) complexity has become one of the most significant obstacles to experimentally demonstrating real-time high-capacity OOFDM transceivers. In this study, extensive numerical explorations are undertaken, for the first time, of the impacts of each individual transceiver DSP element on the inverse error vector magnitude (IEVM) performance of the OOFDM transceivers incorporating full-parallel pipelined FFT/IFFT architectures. More importantly, FFT/IFFT stage-dependent minimum bit resolution maps are identified, based on which minimum bit resolutions of individual DSP elements of various FFT/IFFT stages can be easily selected according to chosen analogue-to-digital converter/digital-to-analogue converter resolutions. The validity and high accuracy of the identified maps are experimentally verified in field programmable gate array (FPGA)-based platforms. In addition to great ease of practical OOFDM transceiver designs, the maps also significantly reduce the FPGA logic resource usage without degrading the overall transceiver IEVM performance.

【 授权许可】

CC BY