Power Integrity Analysis of Low Power SOC Design

2018 2nd annual International Conference on Cloud Technology and Communication Engineering

计算机科学;无线电电子学

Yang, Wu^1 ; He, Xin^1 ; Deng, Jun^1 ; Hu, Keliu^1 ; Huang, Kun^1 ; Fu, Yiru^1

Sichuan Institute of Solid State Circuits, Chongqing, China^1

关键词: Design performance;    Design technologies;    Low-power design;    Placement optimization;    Power integrity;    Power performance;    Problems and challenges;    Structure selection;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/466/1/012060/pdf
DOI  :  10.1088/1757-899X/466/1/012060

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

With the development of process and design technology, the power integrity of low power SOC design meets new problems and challenges. Quantitative analysis is needed to guide the design of power-gating units for low-power SOC design, such as structure selection, the number and size confirmation, and placement optimization. Some new phenomena, such as rush current, rampup time, Power noise coupling and so on, needs to be analyzed and optimized. Static check, dynamic check and powerup analysis are needed to analyze the power performance of low power SOC design. In this paper, ANSYS Redhawk is used to analyze the power integrity of low-power design, and the power performance of low-power SOC design is obtained. Finally, the design of this paper meets the design performance requirements through chip test.