Modeling and Analysis of High-Frequency Microprocessor Clocking Networks

Phase-locked loops;Interlevel coupling noise;Power-performance tradeoff;Skew compensation;Interconnect;Power supply noise;Skew;Clock distribution;Low-power design;Jitter;MOSFET model

Saint-Laurent, Martin ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Phase-locked loops;    Interlevel coupling noise;    Power-performance tradeoff;    Skew compensation;    Interconnect;    Power supply noise;    Skew;    Clock distribution;    Low-power design;    Jitter;    MOSFET model;   

Others  :  https://smartech.gatech.edu/bitstream/1853/7271/1/saint-laurent_martin_200508_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.