Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

International Conference on Recent Trends in Physics 2016

Priydarshi, A.^1 ; Chattopadhyay, M.K.^2

School of Nanotechnology, RGPV Bhopal, India^1

School of Electronics, Devi Ahilya University, Indore, India^2

关键词: Body bias;    Delay;    Double-Gate FinFet;    High performance applications;    High-speed techniques;    Output resistance;    Propagation delays;    Short-channel effect;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/755/1/012055/pdf
DOI  :  10.1088/1742-6596/755/1/012055

来源: IOP

【 摘 要 】

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;