Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

International Conference on Particle Physics and Astrophysics

Vinogradov, S.M.^1 ; Atkin, E.V.^1 ; Ivanov, P.Y.^1

National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Kashirskoe highway 31, Moscow

115409, Russia^1

关键词: CMOS technology;    CMOS transistors;    Design rules;    Engineering calculation;    N-channel transistors;    Parameterized;    Parameterized model;    SPICE modeling;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/675/4/042043/pdf
DOI  :  10.1088/1742-6596/675/4/042043

来源: IOP

【 摘 要 】

The method of creating a parameterized spice model of an N-channel transistor with a gate of enclosed layout is considered. Formulas and examples of engineering calculations for use of models in the computer-aided Design environment of Cadence Vitruoso are presented. Calculations are made for the CMOS technology with 180 nm design rules of the UMC.