Investigation of single-event transient mitigation via pulse quenching in logic circuits

3rd International Conference on Advances in Energy, Environment and Chemical Engineering

能源学;生态环境科学;化学工业

Luo, Sheng^1,2 ; He, Wei^1,2 ; Zhang, Zhun^1,2 ; He, Lingxiang^1,2 ; Cao, Jianmin^2 ; Wu, Qingyang^2

College of Optoelectronic Engineering, Shenzhen University, Shenzhen

518000, China^1

Shenzhen Key Laboratory of Micro-Nano Photonic Information Technology, Shenzhen

518000, China^2

关键词: 65-nm technologies;    Combinational logic circuits;    Layout designs;    Logical circuit;    Single event effects;    Single event transients;   

Others  :  https://iopscience.iop.org/article/10.1088/1755-1315/69/1/012199/pdf
DOI  :  10.1088/1755-1315/69/1/012199

学科分类：环境科学（综合）

来源: IOP

【 摘 要 】

A layout technique which can mitigate single-event effect via pulse quenching is tested in this paper. The new limitation of application of this layout technique is affirmed in 65nm technology. The layout design via pulse quenching has no effects in PMOS, but it can work in NMOS in basic logical circuits. Combinational logic circuits still can use this method to defense single-event effect.