A multi-paradigm C++-based hardware description language

Hardware description language;HDL;Domain-specific language;High-level synthesis

Kersey, Chad Daniel ; Yalamanchili, Sudhakar Kim, Hyesoon Electrical and Computer Engineering Mukhopadhyay, Saibal Conte, Thomas Vuduc, Richard Krishna, Tushar ; Yalamanchili, Sudhakar

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Hardware description language;    HDL;    Domain-specific language;    High-level synthesis;   

Others  :  https://smartech.gatech.edu/bitstream/1853/62342/1/KERSEY-DISSERTATION-2019.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of a core design implemented using this library, are presented. The supporting libraries extend the level of abstraction covered by CHDL from the solely constructive and generative to a range of hardware description paradigms including the register transfer level (RTL), an implementation of Bluespec-like guarded atomic actions (GAA), and a novel pipeline-oriented HDL providing a high-level synthesis flow from algorithmic descriptions of pipelined hardware. Design input using all of these paradigms is converted by CHDL into an in-memory gate level netlist that may be simulated, emitted as synthesizable Verilog, or technology mapped to a standard cell library for area and energy estimation. Access to this netlist, dubbed “netlist introspection”, is provided by the CHDL API, allowing novel optimizations and transformations to be performed by the designer.