Physical design methodologies for monolithic 3D ICs

3D IC;Physical design;Monolithic inter-tier via;Placement;Routing

Panth, Shreepad Amar ; Lim, Sung Kyu Electrical and Computer Engineering Mukhopadhyay, Saibal Raychowdhury, Arijit Kim, Hyesoon Naeemi, Azad J. ; Lim, Sung Kyu

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: 3D IC;    Physical design;    Monolithic inter-tier via;    Placement;    Routing;   

Others  :  https://smartech.gatech.edu/bitstream/1853/53542/1/PANTH-DISSERTATION-2015.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored.Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed.Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences.Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.