Modeling, design, and demonstration of 2.5-D glass interposer packages for high performance computing applications

2.5-D interposer;Electronics packaging;Glass interposer;Multichip modules

Sawyer, Brett Michael Dunn ; Tummala, Rao R. Electrical and Computer Engineering Peterson, Andrew F. Sitaraman, Suresh Brand, Oliver Sundaram, Venkatesh ; Tummala, Rao R.

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: 2.5-D interposer;    Electronics packaging;    Glass interposer;    Multichip modules;   

Others  :  https://smartech.gatech.edu/bitstream/1853/60653/1/SAWYER-DISSERTATION-2017.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The objective of this research is to model, design, fabricate, and characterize high density, die-to-die and high speed, die-to-board interconnections in 2.5-D glass interposer packages for high performance computing applications. The 2.5-D glass interposer package designed in this thesis offers the best combination of low-loss, fine-pitch interconnects and panel-scalable, double-sided fabrication processes to improve signal integrity and to reduce packaging cost compared to wafer-based silicon interposers. Specifically, this thesis addressed two major glass interposer electrical design challenges: (1) high density, die-to-die (wide I/O) interconnects with lower latency than BEOL silicon interconnects, and (2) high speed, die-to-board (external I/O) interconnects with lower attenuation than through silicon via. Modeling, design, fabrication, and characterization of 2.5-D glass interposer RDL demonstrated a 2x reduction in wide I/O latency and a 10x reduction in external I/O attenuation compared to BEOL RDL. This electrical design research was used as a design guideline in the first 2.5-D glass interposer demonstration that integrated RDL and chip assembly processes developed by other researchers to achieve 6 μm pitch RDL and 56 μm chip-level interconnect pitch fabricated on a 100 μm thick 150 mm x 150 mm glass panel with through package via.