学位论文详细信息
| Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures | |
| Electronic packaging;Microelectromechanical systems | |
| Joung, Yeun-Ho ; Electrical and Computer Engineering | |
| University:Georgia Institute of Technology | |
| Department:Electrical and Computer Engineering | |
| 关键词: Electronic packaging; Microelectromechanical systems; | |
| Others : https://smartech.gatech.edu/bitstream/1853/5325/1/joung_yeun-ho_200312_phd.pdf | |
| 美国|英语 | |
| 来源: SMARTech Repository | |
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| Files | Size | Format | View |
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| Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures | 26895KB |  download |
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