Architectural techniques to enable reliable and scalable memory systems

Memory systems;Reliability;Moore's law;Computer architecture;Scaling

Nair, Prashant J. ; Qureshi, Moinuddin K. Electrical and Computer Engineering Yalamanchili, Sudhakar Mukhopadhyay, Saibal Prvulovic, Milos Mutlu, Onur ; Qureshi, Moinuddin K.

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Memory systems;    Reliability;    Moore's law;    Computer architecture;    Scaling;   

Others  :  https://smartech.gatech.edu/bitstream/1853/58309/1/NAIR-DISSERTATION-2017.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

High capacity and scalable memory systems play a vital role in enabling our desk- tops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is seen as the key impediment towards us- ing high-density devices, adopting new technologies, and even building the next Exascale supercomputer. To ensure even a bare-minimum level of reliability, present-day solutions tend to have high performance, power and area overheads. Ideally, we would like memory systems to remain robust, scalable, and implementable while keeping the overheads to a minimum. This dissertation describes how simple cross-layer architectural techniques can provide orders of magnitude higher reliability and enable seamless scalability for memory systems while incurring negligible overheads.