Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

Semiconductors;Electronics;Microsystems;Substrates;Packaging;System on a package

Sundaram, Venkatesh ; Materials Science and Engineering

University:Georgia Institute of Technology

Department:Materials Science and Engineering

关键词: Semiconductors;    Electronics;    Microsystems;    Substrates;    Packaging;    System on a package;   

Others  :  https://smartech.gatech.edu/bitstream/1853/28141/1/sundaram_venkatesh_200905_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.