A Multi-physics approach to the co-design of 3D multi-core processors

Performance;Energy efficiency;3D IC;Multi-core systems;Multi-physics analysis;Microarchitecture co-design

Xiao, He ; Yalamanchili, Sudhakar Electrical and Computer Engineering Joshi, Yogendra Mukhopadhyay, Saibal Wardi, Yorai Kim, Hyesoon ; Yalamanchili, Sudhakar

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Performance;    Energy efficiency;    3D IC;    Multi-core systems;    Multi-physics analysis;    Microarchitecture co-design;   

Others  :  https://smartech.gatech.edu/bitstream/1853/59810/1/XIAO-DISSERTATION-2018.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a single package and enables high integration density. Compared to 2D planar design, 3D ICs shorten the die-to-die distance and substantially increase inter-die communication bandwidth, providing a potential performance boost for large-scale systems. However, the design of 3D multi-core processors exposes great challenges to computer architect. First, 3D ICs create design bottlenecks in thermal management and power delivery. Second, the strong coupling relationship between performance, power, and thermal in 3D ICs adds design complexities. These factors require a holistic view to design high-performance energy-efficient 3D processors. The purpose of the dissertation is to promote a multi-physics co-design methodology in 3D processors that achieves performance gain and energy efficiency. Towards this goal, this dissertation explores the co-design opportunities in a 3D multi-core processor from three perspectives. The first looks into a thermal-architecture co-design, which co-optimizes advanced microfluidic cooling with processor floorplan and power map and develops two high-performance thermally-adaptive processor designs for a given thermal cap. The second focuses on a power-architecture co-design, which minimizes the voltage guardband based on the thermal characterization in SRAM cache and architectural-level prediction for power reduction. The last works on a package-architecture co-design, which designs a Short-Stack structure that mitigates the pin stress problem and proposes a thread scheduling policy for heterogeneous architecture in a 3D package to maximize system performance for a given thermal cap. By evaluating the effectiveness of these approaches, the dissertation underscores the value of the multi-physics co-design as an integral part of future processor design.