Value Communication Techniques to Improve Performance of Transactional Memory Systems.

cache coherence;value prediction;transactional memory;distritbuted systems;memory systems;parallel programming

Pant, Salil Mohan ; Dr Tom Conte, Committee Member,Dr Xiaosong Ma, Committee Member,Dr Eric Rotenberg, Committee Co-Chair,Dr Gregory T. Byrd, Committee Chair,Pant, Salil Mohan ; Dr Tom Conte ; Committee Member ; Dr Xiaosong Ma ; Committee Member ; Dr Eric Rotenberg ; Committee Co-Chair ; Dr Gregory T. Byrd ; Committee Chair

University:North Carolina State University

关键词: cache coherence;    value prediction;    transactional memory;    distritbuted systems;    memory systems;    parallel programming;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/6146/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

Transactional Memory(TM) is an optimistic speculative synchronization scheme that provides atomic execution for a region of code marked as atransaction by the programmer.Programs with critical sections that are not heavily contended benefit from the optimistic nature of TMsystems. However, for heavily contended critical sections, performance for TM systems can degrade due to conflicts leading to stalls andexpensive rollbacks. In this thesis, we investigate methods to improve scalability of TM systems using early value communication (EVC) andunderstand its mechanisms and hardware complexity. We look into the nature of the shared data involved in conflicts for TM systems and find that most transactions have conflicts around a fewshared addresses and shared-conflicting data is often updated in a predictable manner by different transactions.We propose using amemory-level value predictor (VP-TM) to capture this predictability for such data structures and increase overall concurrency by satisfying loads from conflicting transactions with predicted values, instead of stalling. We present one possible design and implementation of TM system with a value predictor. Our benchmark results show us that the value predictor can capture this predictable behavior for most benchmarks and can improve performance of TM programs by improving concurrency and minimizing stalls and rollbacks due to conflicts.To reduce the hardware complexity, we present another design that can provide performance from EVC without the extra hardware costs. Finally, we present a realistic design of the VP-TM system that shows the full impact of the extra hardware and messages and gives us a better idea of performance with VP-TM. Our goal is to increase the adoption of TM for parallel programming by extending the number of applications that can benefit from TM.