Spectral Prediction: A Signals Approach to Computer Architecture Prefetching

Data Prefetching;Autocorrelation;Frequency;Adaptive;Absolute and Differential domain;Cache memory

Sharma, Saurabh ; Thomas M. Conte, Committee Chair,Greg Byrd, Committee Member,Purush Iyer, Committee Member,Eric Rotenberg, Committee Member,Sharma, Saurabh ; Thomas M. Conte ; Committee Chair ; Greg Byrd ; Committee Member ; Purush Iyer ; Committee Member ; Eric Rotenberg ; Committee Member

University:North Carolina State University

关键词: Data Prefetching;    Autocorrelation;    Frequency;    Adaptive;    Absolute and Differential domain;    Cache memory;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/3909/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

Effective data prefetching requires accurate mechanisms to predict embedded patterns in the miss reference behavior. This dissertation introduces a novel technique Spectral Prediction that accurately identifies the pattern by dynamically adjusting to its frequency. The proposed technique exploits the fact that addresses in the reference stream follow definite frequencies and captures them using the recurrence distance information. In so doing, the patterns are successfully detected while the random noise is filtered. This dissertation describes two implementations of spectral prediction: Spectral Prefetcher (SP) and Differential-only Spectral Prefetcher (DOSP). The first implementation, SP, is adaptive in behavior and can capture either the pattern of addresses or the pattern of strides between the addresses within the cache miss stream. SP was designed as a proof-of-concept and provided productive insights for designing a more elegant implementation: DOSP, which is resource-efficient and offers better performance. The dissertation also includes simulation driven performance evaluations of SP and DOSP. Our results show that these implementations of spectral prediction achieve 4% to 400% performance improvement for memory-intensive programs running on an aggressive out-of-order processor with large caches and large branch predictor. Additionally, using a set of co-scheduled pairs of benchmarks on a dual-core CMP, we show that a 16KB on chip implementation of DOSP provides an average throughput improvement of 10% and at best by 86%.