Performance Analysis of System-on-Chip Applications of Three-dimensional Integrated Circuits

OpenRISC 1200 Architecture;3D IC Design Flow;Three-dimensional integration;3D IC;3D SoC Design;Temperature Dependent Circuit Modeling;3D Power Dissipation and Critical Path Delay Analy;FDSOI 3D Process;MOSFET temperature effects;3D interconnect;3D circuits;3D physical design

Schoenfliess, Kory Michael ; Dr. W. Rhett Davis, Committee Chair,Dr. Paul Franzon, Committee Member,Dr. Douglas Barlage, Committee Member,Schoenfliess, Kory Michael ; Dr. W. Rhett Davis ; Committee Chair ; Dr. Paul Franzon ; Committee Member ; Dr. Douglas Barlage ; Committee Member

University:North Carolina State University

关键词: OpenRISC 1200 Architecture;    3D IC Design Flow;    Three-dimensional integration;    3D IC;    3D SoC Design;    Temperature Dependent Circuit Modeling;    3D Power Dissipation and Critical Path Delay Analy;    FDSOI 3D Process;    MOSFET temperature effects;    3D interconnect;    3D circuits;    3D physical design;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/2481/etd.pdf?sequence=1&isAllowed=y

美国|英语

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【 摘 要 】

In the research community, three-dimensional integrated circuit (3DIC) technology has garnered attention for its potential use as a solution to the scaling gap between MOSFET device characteristics and interconnects. The purpose of this work is to examine the performance advantages offered by 3DICs. A 3D microprocessor-based test case has been designed using an automated 3DIC design flow developed by the researchers of North Carolina State University. The test case is based on an open architecture that is exemplary of future complex System-on-Chip (SoC) designs.Specialized partitioning and floorplanning procedures were integrated into the design flow to realize the performance gains of vertical interconnect structures called 3D vias. For the post-design characterization of the 3DIC, temperature dependent models that describe circuit performance over temperature variations were developed. Together with a thermal model of the 3DIC, the performance scaling with temperature was used to predict the degree of degradation of the delay and power dissipation of the 3D test case. Using realistic microprocessor workloads, it was shown that the temperatures of the 3DIC thermal model are convergent upon a final value. The increase in delay and power dissipation from the thermal analysis was found to be negligibly small when compared to the performance improvements of the 3DIC. Timing analysis of the 3D design and its 2D version revealed a critical path delay reduction of nearly 26.59% when opting for a 3D implementation.In addition, the 3D design offered power dissipation savings of an average of 3% while running at a proportionately higher clock frequency.