As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic design automation), such as lack of effective tools for analog circuit or high-volume and high-frequency printed circuit board (PCB) design, the contradiction between complex EDA compute workloads andtime-to-market pressure,manufacturing variability and powermanagement, to name but a few. In this dissertation, we will proposeseveral new strategies to handle the challenges in the EDA field.Wire routing is an important step in the design of PCBs. Althoughthere are many industrial tools to handle IC routing problems, veryfew tools can handle the routing on high-density and high-frequencyboards effectively. Nowadays, most of the PCB routing is still doneby tedious and time-consuming manual work. We provide new strategies to solve an important problem in PCB routing, the escape routing problem. Our first strategy is to use Boolean satisfiability to optimally solve the escape routing problem on one PCB component. Our second strategy is to use a novel boundary routing methodology to finish escape routing from two connected PCB components simultaneously. This router can achieve much better routability than industrial tools with less CPU time.Another challenge seen in the EDA field is the increasing CPU timeto handle larger and larger designs. On the other hand, manyfundamental algorithms and data structures used in the EDA toolshave shown great parallelism, such as the well-known BFS (breadth-first search) algorithm and the R-tree structure. Therefore, we propose strategies to use the cost-effective GPU platform to parallelize and accelerate BFS and R-tree query. These strategies are potentially applicable to many EDA problems.
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