FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs(application-specific integrated circuits) for significantly lowering amortized manufacturing costsand dramatically improving design productivity. The architecture of an FPGA is very regular. It isrelatively easy to design a highly optimized tile, with consideration of various manufacturingrelated issues, and then to replicate it many times across the chip. The configurability of FPGAsalso enables yield improvement and defect tolerance. However, FPGAs are still facing seriouschallenges in terms of delay, power consumption, and logic density compared to ASICs. FPGA isestimated to be over twenty times less efficient in logic density, over three times worse in delay,and over ten times higher in power consumption compared to a functionally equivalent ASIC.One promising way to improve FPGA performance is to incorporate three-dimensional(3D) integration, which increases the number of active layers and optimizes the interconnectnetwork vertically. Another solution is to apply novel nanoelectronic materials (nanomaterials)and devices. This dissertation introduces three novel reconfigurable architectures, named 3DnFPGA, FPCNA (field programmable carbon nanotube array), and NEM FPGA(nanoelectromechanical FPGA), which utilize 3D integration techniques and new nanoscalematerials synergistically. Customized CAD flows that consider process variation have beendeveloped for different architectures to evaluate their potential performances. Also described is a3D variation aware routing flow, which is an essential tool for future 3D FPGA architectureexploration.3D nFPGA is based on CMOS (complementary metal-oxide-semiconductor) and nanohybrid techniques that incorporate nanomaterials such as nanowire crossbars and carbonnanotube bundles into the CMOS fabrication process. Using unique features of FPGAs and anovel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4×footprint reduction comparing to the traditional CMOS-based 2D FPGAs. The performance and power of 3D nFPGA driven by the 20 largest MCNC (microelectronics center of North Carolina)benchmarks have been evaluated. Results demonstrate that 3D nFPGA is able to provide aperformance gain of 2.6× with a small power overhead compared to the traditional 2D FPGA.FPCNA includes lookup tables created entirely from continuous carbon nanotube (CNT)ribbons. To determine the performance of the building blocks, variation aware physical designtools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian andnon-Gaussian random variables. A 2.75× performance improvement is seen over an equivalentCMOS FPGA at a 95% yield. In addition, FPCNA offers a 5× footprint reduction compared to abaseline FPGA.3D NEM FPGA is the architecture that utilizes nanoelectromechanical (NEM) relays and3D integration techniques synergistically. This proposed architecture has unique featuresincluding a hybrid CMOS-NEM FPGA lookup table (LUT) and configurable logic block (CLB),NEM-based switch block (SB) and connection block (CB), and face-to-face 3D stacking. Thisarchitecture also has a built-in feature called direct link, which takes advantage of the shortvertical wire length provided by 3D stacking to further enhance performance. An overall 46.3%critical path delay reduction has been observed compared to its CMOS counterpart.To maximize the potential performance gain of 3D integrated circuit architectures, anSSTA engine was developed to deal with both uncorrelated and correlated variations in 3DFPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physicaldesign tool TPR as a base, a new 3D routing algorithm is developed, which improves the averageperformance of two-layer designs by over 22% and three-layer designs by over 27%.
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