Architecture Independent Timing Speculation Techniques in VLSI Circuits.

VLSI;Digital Circuits;Timing Speculation;Variation Tolerance;Two-Phase Latches;Razor;Electrical Engineering;Engineering;Electrical Engineering

Fojtik, Matthew R.Mudge, Trevor N. ;

University of Michigan

关键词: VLSI;    Digital Circuits;    Timing Speculation;    Variation Tolerance;    Two-Phase Latches;    Razor;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/102461/mfojtik_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Conventional digital circuits must ensure correct operation throughout a wide range of operating conditions including process, voltage, and temperature variation.These conditions have an effect on circuit delays, and safety margins must be put in place which come at a power and performance cost.The Razor system proposed eliminating these timing margins by running a circuit with occasional timing errors and correcting the errors when they occur.Several existing Razor style designs have been proposed, however prior to this work, Razor could not be applied blindly or automatically to designs, as the various error correction schemes modified the architecture of the target design.Because of the architectural invasiveness and design complexities of these techniques, no published Razor style system had been applied to a complete existing commercial processor. Additionally, in all prior Razor-style systems, there is a fundamental tradeoff between speculation window and short path, or minimum delay, constraints, limiting the technique’s effectiveness. This thesis introduces the concept of Razor using two-phase latch based timing.By identifying and utilizing time borrowing as an error correction mechanism, it allows for Razor to be applied without the need to reload data or replay instructions.This allows for Razor to be blindly and automatically applied to existing designs without detailed knowledge of internal architecture.Additionally, latch based Razor allows for large speculation windows, up to 100% of nominal circuit delay, because it breaks the connection between minimum delay constraints and speculation window.By demonstrating how to transform conventional flip-flop based designs, including those which make use of clock gating, to two-phase latch based timing, Razor can be automatically added to a large set of existing digital designs.Two forms of latch based Razor are proposed.First, Bubble Razor involves rippling stall cycles throughout a circuit in response to timing errors and is applied to the ARM Cortex-M3 processor, the first ever application of a Razor technique to a complete, existing processor design.Additional work applies Bubble Razor to the ARM Cortex-R4 processor.The second latch based Razor technique, Voltage Razor, uses voltage boosting to correct for timing errors.