Digitally Assisted ADCS.

ADC;CMOS;Calibration;Folding;DAC;Electrical Engineering;Engineering;Electrical Engineering

Bogue, Ivan TimothyWentzloff, David Dale ;

University of Michigan

关键词: ADC;    CMOS;    Calibration;    Folding;    DAC;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/58426/ibogue_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

This work involves the development of digital calibration techniques for Analogto-Digital Converters. According to the 2001 International Technology Roadmap forSemiconductors, improved ADC technology is a key factor in the development of presentand future applications.The switched-capacitor (SC) pipeline technique is the most popular method ofimplementing moderate resolution ADCs. However the advantages of CMOS, whichoriginally made SC circuits feasible, are being eroding by process scaling. Good switchesand opamps are becoming increasingly difficult to design and the growing gate leakageof deep submicron MOSFETs is causing difficulty. Traditional ADC schemes do notwork well with supply voltages of 1.8V and below. Furthermore, the performance required by present and future wireless and IT applications will not be met by the presentday ADC circuits techniques.Bearing in mind the challenges associated with deep sub-micron analog circuitrya new calibration technique for folding ADCs has been developed. Since digital circuitryscales well, this calibration relies heavily on digital techniques. Hence it reduces theamount of analog design involved. As this folding ADC is dominated, in terms of bothfunctionality and power, by digital circuitry, the performance of folding will improvewhen implemented in smaller geometry processes.An 8-bit, 500MS/s, digitally calibrated folding ADC was designed in TSMC0.18mm. A second prototype, 9-bit 400MS/s, was designed in ST 90nm. This ADC usesnovel folders to reduce thermal noise.The major accomplishments of this work are:· The creation of a new folding ADC architecture that is digitally dominatedallowing large transistor mismatch to be tolerated so that small devicescan be utilized in the signal path.· The development of modeling techniques, to investigate and analyze theeffects of transistor mismatch, folder linearity and redundancy in ADCs.· The design of a new folder circuit topology that decreases the requiredpower consumption for a given noise budget.· The design of a resistor ladder DAC that uses a unique resistor layout toallow any shape ladder to be designed.