Manufacturability Aware Design.

Design for Manufacturability (DFM);Physical Design;Process Variation;Timing Analysis;Timing-driven OPC;Restrictive Design Rule (RDR);Flexible Design Rule (FDR);DRC Plus;Pattern Matching;Electrical Engineering;Engineering;Electrical Engineering

Yang, JieWise, Kensall D. ;

University of Michigan

关键词: Design for Manufacturability (DFM);    Physical Design;    Process Variation;    Timing Analysis;    Timing-driven OPC;    Restrictive Design Rule (RDR);    Flexible Design Rule (FDR);    DRC Plus;    Pattern Matching;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/57676/jiey_1.pdf?sequence=2&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

The aim of this work is to provide solutions that optimize the tradeoffs among design, manufacturability, and cost of ownership posed by technology scaling and sub-wavelength lithography. These solutions may take the form of robust circuit designs, cost-effective resolution technologies, accurate modeling considering process variations, and design rules assessment. We first establish a framework for assessing the impact of process variation on circuit performance, product value and return on investment on alternative processes. Key features include comprehensive modeling and different handling on die-to-die and within-die variation, accurate models of correlations of variation, realistic and quantified projection to future process nodes, and performance sensitivity analysis to improved control of individual device parameter and variation sources. Then we describe a novel minimum cost of correction methodology which determines the level of correction of each layout feature such that the prescribed parametric yield is attained with minimum RET (Resolution Enhancement Technology) cost. This timing driven OPC (Optical Proximity Correction) insertion flow uses a mathematical programming based slack budgeting algorithm to determine OPC level for all polysilicon gate geometries. Designs adopting this methodology show up to 20% MEBES (Manufacturing Electron Beam Exposure System) data volume reduction and 39% OPC runtime improvement. When the systematic correction residual errors become unavoidable, we analyze their impact on a state-of-art microprocessor;;s speedpath skew. A platform is created for diagnosing and improving OPC quality on gates with specific functionality such as critical gates or matching transistors. Significant changes in full-chip timing analysis indicate the necessity of a post-OPC performance verification design flow. Finally, we quantify the performance, manufacturability and mask cost impact of globally applying several common restrictive design rules. Novel approaches such as locally adapting FDRs (flexible design rules) based on image parameters range, and DRC Plus (preferred design rule enforcement with 2D pattern matching) are also described.