SPi User Manual V0.1

Trimpl, M. ; Yarema, R. ; /Fermilab ; Newcomer, M. ; Dressnandt, N. ; /Pennsylvania U. ; Villani, G. ; Weber, M. ; Holt, R. ; /Rutherford

关键词: BUFFERS;    BYPASSES;    DESIGN;    RADIATIONS;    SILICON;    SPIN;    TRANSISTORS Accelerators;    Computing;   

DOI  :  10.2172/1030701
RP-ID  :  FERMILAB-TM-2496-E
PID  :  OSTI ID: 1030701
Others  :  TRN: US1200063

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来源: SciTech Connect

【 摘 要 】

This document describes the Serial Powering Interface (SPi) ASIC. SPi is a general purpose ASIC prototype designed for use in serial powering of silicon detector instrumentation. This description is written as a user manual to aid application, not as a design description. SPi is a generic custom ASIC, manufactured in 0.25 {mu}m CMOS by TSMC, to interface between a constant current source and silicon detector read-out chips. There is no SEU (single event upset) protection, but most (not all) components are radiation tolerant design. An operating voltage of 1.2 to 2.5 volts and other design features make the IC suitable for a variety of serial powering architectures and ROICs. It should be noted that the device is likely to be a prototype for demonstration rather than a product for inclusion in a detector. The next design(s), SPin, are likely to be designed for a specific application (eg SLHC). The component includes: (1) Seven bi-directional LVDS-like buffers for high data rate links to/from the read-out chips. These are AC coupled (series capacitor) off-chip for DC level conversion; (2) A programmable internal programmable shunt regulator to provide a defined voltage to readout chips when linked in a serial powering chain; (3) A programmable internal shunt regulator control circuit for external transistor control; (4) Shunt current measurement (for internal shunt regulator); (5) A programmable internal shunt regulator current alarm; and (6) Two programmable linear regulators.