Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

Indian Journal of Pure & Applied Physics

article

Rupali Singha¹  Pankaj Singh²  Gurmohan Singh³ 

[1] Department of Electronics and Communication Engineering, SRM Institute of Science and Technology;Department of Electrical Engineering, IIMT University;Centre for Development of Advanced Computing

关键词: QCA;    PLA;    Decoder;    Adder;    Subtractor;    Article;   

DOI  :  10.56042/ijpap.v60i10.63908

来源: National Institute of Science Communication and Information Resources

【 摘 要 】

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

【 授权许可】

Unknown