Performance Analysis of a High-Speed High-Precision Dynamic Comparator

Indian Journal of Pure & Applied Physics

article

Vaithiyanathan Dhandapani¹  Ashish Mishra¹  Ankit Kumar¹  Alok Kumar Mishra¹  Sachin Singh¹  Baljit Kaur¹ 

[1] Department of Electronics and Communication Engineering, National Institute of Technology Delhi

关键词: Dynamic comparator;    Preamplifier;    low-power analog design;    high speed;    low-offset;    analog-to-digital-converters (ADCs);    Article;   

来源: National Institute of Science Communication and Information Resources

【 摘 要 】

Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.

【 授权许可】

Unknown