Power and Area Minimization of Reconfigurable FFT Processor using Distributed Arithmetic

Research & Reviews: Journal of Engineering and Technology

article

Anuradha M¹  Vishal R¹ 

[1] Electronics & Telecommunication Engineering Department, SavitribaiPhule, Pune University

关键词: Digital signal processing (DSP);    Complex multiplier;    Distributed Arithmetic;    FFTs.;   

来源: Research & Reviews

【 摘 要 】

Fast Fourier transforms is one of the most important frequency analysis in signal processing. It has different application such as image processing, medical field, communication system, spectral analysis etc. Butterfly is the basic elements of FFT. In this work a Distributed arithmetic technique is used to implement the butterfly module. Distributed arithmetic is Multiplierless technique resulted more efficient butterfly element both in terms of power and area. Butterfly element is the most important building block of Reconfigurable FFT processor. Single precision is used to represent the data. IEEE 754 standard is used to represent the floating point numbers.

【 授权许可】

Unknown