A High Performance Decimal Matrix CodeArchitecture for Improved Reliable Memory

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

M. Satya sri¹  K.Jyothi¹ 

[1] Dept. of ECE, GIET

关键词: Error correction codes (ECCs);    multiple cells upsets (MCUs);    memory.;   

DOI  :  10.15662/ijareeie.2014.0310043

来源: Research & Reviews

【 摘 要 】

Protection codes are necessary to shield memory cells, to maintain good quality level of reliability. But, we don’t find any optimized error detection and correction methods. Therefore, in this paper, we present a high performance Decimal Matrix Code to assure the reliability of memory. This protection code utilizes decimal procedure to detect errors, so that more errors were detected and corrected up to 32. Transient multiple cell upsets (MCUs) are major problems in the reliability of memories exposed to radiation environment. To prevent cell upsets from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but they would require higher delay so an efficient ERT (encoder-reuse technique) is proposed to reduce the area overhead of extra circuits, it utilize DMC encoder itself to be part of the decoder.

【 授权许可】

Unknown