A Low Power Comparator Design for 6-BitFlash ADC in 90-Nm CMOS

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Parthasarathy K P¹  K C Narasimhamurthy¹ 

[1] Dept. of TCE, Siddaganga Institute of Technology

关键词: Flash ADC;    Preamplifier based latch Comparator;    Low power consumption.;   

来源: Research & Reviews

【 摘 要 】

The main focus of this paper is to design a “Low power Flash ADC” for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, Fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper is designed using 90nm technology at 0.8V DC voltage source using H SPICE tool. The Simulation results of a 6-bit flash ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW.

【 授权许可】

Unknown