A 40.0 GS/S TIME INTERLEAVED 6 BIT FLASHADC FOR 40GBE APPLICATIONS

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Shahir P¹  V. Jean Shilpa¹ 

[1] Department of Electronics and Communication, B.S. Abdur Rahman University

关键词: Flash ADC;    Analog demultiplexing;    high-speed comparator;    time-domain latch interpolation;    Time interleaved ADC;   

来源: Research & Reviews

【 摘 要 】

This paper presents the analog back end design of a 40-GS/s 6-bit Flash ADC for 40GbE applications. It is designed in a 45 nm CMOS technology on the basis of a 16-fold time-interleaving procedure. In this work a 6-b 2.5 - GS/s flash ADC was designed (which is used for time interleaving) with a time-domain latch interpolation method that reduces the number of dynamic comparators used in the first stage of ADC by half. The reduced number of comparators lowers load capacitance to the sample and hold circuit, power consumption and the overhead of comparator calibration. The measured peak DNL and INL are 0.53 and 0.61 LSB, respectively. The calculated SFDR and SNDR are 42.1 and 33.3 dB, and the power consumption is about 69mW.

【 授权许可】

Unknown