期刊论文详细信息
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
128-BIT CARRY SELECT ADDER HAVINGLESS AREA AND DELAY
article
M.CHITHRA1  G.OMKARESWARI2 
[1] Dept. of ECE, Sri Venkateshwara Engineering College;Dept. of ECE Sri Venkateshwara Engineering College
关键词: Application-specific integrated circuit (ASIC);    area-efficient;    CSLA;    low delay.;   
来源: Research & Reviews
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【 摘 要 】

Design of low area, delay and power forms the largest systems in VLSI system design. Carry Select Adder (CSLA) is one of the fastest adders to perform arithmetic operations comparing all conventional adders. From the structure of CSLA there is a scope for reducing the area and delay. Based on the modification of 16, 32, and 64-bit Carry Select Adder (CSLA) architectures have been developed and compared with the regular CSLA architecture. A carry-select adder (CSLA) can be implemented by using Ripple carry adder. The proposed design 128-bit CSLA has reduced more delay and area as compared with the regular 128-bit CSLA. Results obtained from modified carry select adders are better in area, delay and power consumption.

【 授权许可】

Unknown   

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