A multi-level architecture for hardware Trojan and vulnerability runtime detection and response towards cryptographic IP

IEICE Electronics Express

article

Zhaojie Dong¹  Lan Chen¹  Ying Li¹ 

[1] Institute of Microelectronics of Chinese Academy of Sciences;School of Integrated Circuits, University of Chinese Academy of Sciences;Beijing Key Laboratory of Three-Dimensional and Nanometer Integrated Circuit Design Automation Technology

关键词: cryptographic IP;    hardware bug;    hardware Trojan;    detection;    response;    security architecture;   

DOI  :  10.1587/elex.19.20220167

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

Existing functional validation approaches and post-manufacturing tests are inadequate to detect all hardware bugs and hardware Trojans in third-party intellectual property blocks (3PIPs). Especially for cryptographic IPs, a well-designed framework is needed for detecting and mitigating hardware security risks even after chip deployment. In this paper, we present an innovative multi-level architecture providing runtime hardware security detection and response. The proposed architecture consists of a controller and a security wrapper, enabling the collaborative operation of three different types of detection and three levels of response according to the potential malicious impact. We show that a field programmable gate array prototype of the proposed architecture can pursue 4 hardware bug and 6 hardware Trojan detection towards an AES IP, and make appropriate protective responses.

【 授权许可】

CC BY