Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS

Article

Rakshit, Joydeep¹  Mohanram, Kartik¹  Wan, Runlai^2,3  Lam, Kai Tak^2,3  Guo, Jing^2,3 

[1] Univ Pittsburgh, Pittsburgh, PA 15213 USA.;Univ Florida, Gainesville, FL 32610 USA.;Univ Florida, Dept Elect & Comp Engn, 551 New Engn Bldg,POB 116130, Gainesville, FL 32611 USA.

关键词: Monolayer FET SRAM;    static power;    noise margins;    process variations;    SUBTHRESHOLD SRAM;    BLACK PHOSPHORUS;    DESIGN;    TECHNOLOGY;    CIRCUITS;   

DOI  :  10.1145/2967613

来源: SCIE

【 摘 要 】

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMD-CFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high ION/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent devicemodeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.

【 授权许可】

Free