A Cell Sizing Technique for Mitigating Logic Soft Errors in Gate-level Designs

Advances in Electrical and Computer Engineering

关键词: single event transient;    soft error;    soft error mitigation;    gate-level;    gate sizing;    cell sizing;   

DOI  :  10.4316/AECE.2013.04003

来源: DOAJ

【 摘 要 】

The effect of logic soft errors on the degradation of the reliability becomes more crucial in the caseof nano-meter semiconductor designs. Several hardening techniques have been reported from thetransistor- to system-level. In order to suppress the single event transients originating fromlogic gates, this paper presents an improved heuristic search utilizing the gate-sizing technique.The algorithm re-orders the gate-traversal to maintain the reduced soft error rates of the precedinglogic gates. The preferential candidates for the two successive algorithms are the logic gates nearthe primary outputs and flip-flops, rather than those of the higher portions of block soft error rate.The proposed technique reduces the logic soft error rate by more than 60% compared to the existingmethod in 45nm CMOS cell designs.

【 授权许可】

Unknown