A Cell Sizing Technique for Mitigating Logic Soft Errors in Gate-level Designs

Advances in Electrical and Computer Engineering

PARK, J. K. ; KIM, J. T..

关键词: single event transient;    soft error;    soft error mitigation;    gate-level;    gate sizing;    cell sizing;   

DOI  :  10.4316/AECE.2013.04003

学科分类：计算机科学（综合）

来源: Universitatea "Stefan cel Mare" din Suceava

【 摘 要 】

The effect of logic soft errors on the degradation of the reliability becomes more crucial in the case of nano-meter semiconductor designs. Several hardening techniques have been reported from the transistor- to system-level. In order to suppress the single event transients originating from logic gates, this paper presents an improved heuristic search utilizing the gate-sizing technique. The algorithm re-orders the gate-traversal to maintain the reduced soft error rates of the preceding logic gates. The preferential candidates for the two successive algorithms are the logic gates near the primary outputs and flip-flops, rather than those of the higher portions of block soft error rate. The proposed technique reduces the logic soft error rate by more than 60% compared to the existing method in 45nm CMOS cell designs.

【 授权许可】

Unknown