The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences

Min-Su Kim¹  Hyungmo Koo²  Hansik Oh²  Youngoo Yang² 

[1] Department of Digital Electronics, Dealim University College, 29 Imgok-ro, Dongan-gu, Anyang-si, Gyeonggi-do 13916, Korea;Department of Electrical and Computer Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do 16419, Korea;

关键词: serial to parallel converter;    digital controller;    embedded system;    embedded hardware system;    5G;    RF Front-End;   

DOI  :  10.3390/app11010429

来源: DOAJ

【 摘 要 】

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S²P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S²P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm² and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

【 授权许可】

Unknown