A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials

Electronics

Ruzica Jevtic¹  Abraham Otero¹  David G. Márquez¹  Gabriel Caffarena¹  Madhav P. Desai² 

[1] Department of Information Technologies, University CEU San Pablo, 28003 Madrid, Spain;Indian Institute of Technology (Bombay), Mumbai 400076, India;

关键词: ECG;    real-time;    FPGA;    HLS;    AHIR;    Hermite;   

DOI  :  10.3390/electronics10192324

来源: DOAJ

【 摘 要 】

Automatic ECG signal characterization is of critical importance in patient monitoring and diagnosis. This process is computationally intensive, and low-power, online (real-time) solutions to this problem are of great interest. In this paper, we present a novel, dedicated hardware implementation of the ECG signal processing chain based on Hermite functions, aiming for real-time processing. Starting from 12-bit ADC samples of the ECG signal, the hardware implements filtering, peak and QRS detection, and least-squares Hermite polynomial fit on heartbeats. This hardware module can be used to compress ECG data or to perform beat classification. The hardware implementation has been validated on a Field Programmable Gate Array (FPGA). The implementation is generated using an algorithm-to-hardware compiler tool-chain and the resulting hardware is characterized using a low-cost off-the-shelf FPGA card. The single-beat best-fit computation latency when using six Hermite basis polynomials is under 1 s with a throughput of 3 beats/s and with an average power dissipation around 28 mW, demonstrating true real-time applicability.

【 授权许可】

Unknown