FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

Electronics

Ihab Adly¹  HassaneinH. Amer²  GehadI. Alkady²  Ahmed Hussien³  ManarN. Shaker³ 

[1] Electrical Engineering Department, The British University in Egypt (BUE), Cairo 11837, Egypt;Electronics and Communications Engineering Department, American University in Cairo, Cairo 11835, Egypt;Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt;

关键词: FPGA;    single event upset (SEU);    multiple event upsets (MEUs);    automotive;    fault tolerance;    fault secure;   

DOI  :  10.3390/electronics9122064

来源: DOAJ

【 摘 要 】

Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

【 授权许可】

Unknown