An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

Symmetry

MajedM. Alhaisoni¹  Muhammad Awais²  Omer Chughtai²  SyedRameez Naqvi²  Ali Roman²  Muhammad Naeem²  SajjadAli Haider²  Tallha Akram² 

[1] College of Computer Science and Engineering, University of Ha′il, Ha′il 81451, Saudi Arabia;Department of Electrical and Computer Engineering, COMSATS University Islamabad, Wah Cantonment 47040, Pakistan;

关键词: computer organization;    mathematical programming;    optimization;    modeling;    performance evaluation;    dynamic partial reconfiguration;   

DOI  :  10.3390/sym11070938

来源: DOAJ

【 摘 要 】

Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

【 授权许可】

Unknown