Three abstraction levels based low overhead scheme of multiple bit upsets mitigation for FPGA

Dianzi Jishu Yingyong

Zhang Xiaolin¹  Ding Lei¹  Gu Liming¹ 

[1] No.36 Research Institute of CETC，Jiaxing 314033，China;

关键词: fault tolerance;    multiple bit upsets(MBU);    dynamic partial reconfiguration(DPR);    temporal redundancy;   

DOI  :  10.16157/j.issn.0258-7998.174184

来源: DOAJ

【 摘 要 】

Commercial-off-the-shelf(COTS) FPGAs are often advocated as the only solution to the increasing performance requirements in space applications. It also increases the circuit sensitivity to multiple bit upsets(MBU), thus specific design techniques must be applied to compensate this effect. This work tackles fault tolerance along three abstraction levels: user logic, configuration memory and control. At the user logic level, a new ultra-low overhead forward temporal redundancy(FTR) scheme is proposed for error detection in user logic. At the configuration memory level in the FPGA, this work leverages the opportunities brought by frame- and module-based dynamic partial reconfiguration(DPR) to handle configuration memory errors. At the control level, this work fully exploits the modern Xilinx ZYNQ system-on-chip FPGA which embeds a hard processor used for circuit state preservation with checkpointing and rollback. The overall topology is successfully validated with 99.997% reliability through fault-injection for a seven pipelined LEON3 processor at a global resource overhead only 85% in LUTs and 125% in flip-flops.

【 授权许可】

Unknown