Simple generation of threshold for images binarization on FPGA

Ingeniería e Investigación

Egidio Ieno¹  Luis Manuel Garcés²  Alejandro José Cabrera²  Tales Cleber Pimenta³ 

[1] Centro Federal de Educação Tecnológica (CEFET).;Instituto Superior Politécnico “José Antonio Echeverría” (CUJAE).;Universidade Federal de Itajubá (UNIFEI).;

关键词: Digital image processing;    threshold;    FPGA;    System Generator®;    MATLAB®/Simulink®.;   

DOI  :  10.15446/ing.investig.v35n3.51750

来源: DOAJ

【 摘 要 】

This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.

【 授权许可】

Unknown