A Highly Configurable High-Level Synthesis Functional Pattern Library

Electronics

Zihao Wang¹  Teng Gao¹  Dalin Li¹  Lan Huang¹  Kangping Wang¹ 

[1] College of Computer Science and Technology, Jilin University, Changchun 130012, China;

关键词: field programmable gate arrays;    parallel programming;    C++ template;    functional programming;    pipeline processing;   

DOI  :  10.3390/electronics10050532

来源: DOAJ

【 摘 要 】

FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.

【 授权许可】

Unknown