Low-Latency Lattice-Reduction-Aided One-Bit Precoding Processor for 64-QAM 4×64 MU–MIMO Systems

IEEE Open Journal of Circuits and Systems

Chiao-En Chen¹  Yuan-Hao Huang²  Pao-Pao Ho² 

[1] Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan;Institute of Communications Engineering, National Tsing Hua University, Hsinchu, Taiwan;

关键词: Lattice reduction;    multi-user MIMO;    one-bit precoding;    VLSI;   

DOI  :  10.1109/OJCAS.2021.3087482

来源: DOAJ

【 摘 要 】

Massive multi-user multiple-input multiple-output (MU-MIMO) communication is a crucial technique for next-generation wireless systems because it enables high-throughput and ultra-reliable data transmission. However, high power consumption is a challenging problem in conventional transceiver designs, where each RF chain at the transmitter requires a pair of high-resolution digital-to-analog converters (DACs), which are the primary power sources in front-end circuits. Therefore, quantized precoding algorithms were recently proposed to address this issue. They used low-resolution DACs at the transmitter and compensated for the distortion caused by the quantization effect at the baseband. This paper proposes a constellation-range gain-controlled lattice-reduction-aided (CR-GCLRA) one-bit precoding algorithm for massive MU-MIMO systems with high-order quadrature amplitude modulation (QAM) signaling. Lattice reduction (LR) preprocessing is adopted for performance enhancement. A novel gain-control mechanism is proposed to address the constellation range expansion problem in conventional LR preprocessing. We designed and implemented a CR-GCLRA one-bit precoding processor by using TSMC 40-nm CMOS technology to accelerate the one-bit precoding processing for 64-QAM $4 \times 64$ MU-MIMO system. The proposed one-bit precoding processor can achieve a throughput of 43.92 Mbits per second at a clock speed of 269 MHz with 271 mW power consumption and $0.51\mu \text{s}$ latency.

【 授权许可】

Unknown