Lattice reduction for MIMO detection: from theoretical analysis to hardware realization

MIMO;Wireless;Lattice reduction;VLSI;Hardware;FPGA

Gestner, Brian Joseph ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: MIMO;    Wireless;    Lattice reduction;    VLSI;    Hardware;    FPGA;   

Others  :  https://smartech.gatech.edu/bitstream/1853/39591/1/gestner_brian_j_201105_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The objective of the dissertation research is to understand the complexinteraction between the algorithm and hardware aspects of symboldetection that is enhanced by lattice reduction (LR) preprocessing forwireless MIMO communication systems. The motivation for this work stemsfrom the need to improve the bit-error-rate performance of conventional,low-complexity detectors while simultaneously exhibiting considerablyreduced complexity when compared to the optimal method, maximumlikelihood detection. Specifically, we first develop an understanding ofthe complex Lenstra-Lenstra-Lovász (CLLL) LR algorithm from a hardwareperspective.This understanding leads to both algorithm modificationsthat reduce the required complexity and hardware architectures that arespecifically optimized for the CLLL algorithm. Finally, we integratethis knowledge with an understanding of LR-aided MIMO symbol detectionin a highly-correlated wireless environment, resulting in a jointLR/symbol detection algorithm that maps seamlessly to hardware. Hence,this dissertation forms the foundation for the adoption of latticereduction algorithms in practical, high-throughput wireless MIMOcommunications systems.