Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Sensors

Miron Kłosowski¹  Yichuang Sun² 

[1] Faculty of Electronics, Telecommunications and Informatics, Gdańsk University of Technology, 11/12 Gabriela Narutowicza Street, 80-233 Gdańsk, Poland;School of Engineering and Computer Science, University of Hertfordshire, Hatfield, Herts AL10 9AB, UK;

关键词: image sensor;    fixed pattern noise;    gain correction;    offset correction;    integral nonlinearity correction;    time-mode ADC;   

DOI  :  10.3390/s20205921

来源: DOAJ

【 摘 要 】

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

【 授权许可】

Unknown