Negative capacitance δ -bulk planar junctionless transistor for low power applications

Micro & nano letters

article

Khemnand B. Bhagat¹  Ganesh C. Patil¹ 

[1] Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology

关键词: ferroelectric materials;    semiconductor device models;    leakage currents;    semiconductor doping;    field effect transistors;    low-power electronics;    bulk region;    ferroelectric layer;    low-power applications;    substrate doping;    short-channel effects;    bulk-planar junctionless transistor;    NCδ-BPJLT;    off-state leakage current;    sub-threshold slope;    BPJLT heavily doped δ-layer;    negative capacitance δ-BPJLT;    ferroelectric material;    size 10.0 nm;   

DOI  :  10.1049/mnl.2019.0153

学科分类：计算机科学（综合）

来源: Wiley

【 摘 要 】

The impact of substrate doping on the short-channel effects (SCEs) of bulk-planar junctionless transistor (BPJLT) has been studied. It has been found that increasing substrate doping in bulk region reduces off-state leakage current ( I OFF ) and the sub-threshold slope (SS ) of the device. To further reduce the SCEs of BPJLT heavily doped δ -layer of thickness 10 nm has been added below the channel. Despite the presence of δ -layer in BPJLT reduces SCEs, the SCE, mainly SS, is still limited by the fundamental limit of 60 mV/decade. Therefore, to reduce SS below 60 mV/decade, negative capacitance (NC) δ -BPJLT has been proposed by adding the layer of ferroelectric material at gate stack. It has been found that in comparison with conventional BPJLT and δ -BPJLT, the insertion of ferroelectric layer in NC- δ -BPJLT not only reduces the I OFF and the SS but also improves I ON / I OFF ratio of the device. Thus, embedding heavily doped δ -layer in the bulk region and the ferroelectric layer at the gate stack of BPJLT makes it a promising device for low-power applications.

【 授权许可】

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