0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process

Journal of Low Power Electronics and Applications

Piotr Olejarz¹  Kyoungchul Park²  Samuel MacNaughton²  Mehmet R. Dokmeci³ 

[1] Electrical and Computer Engineering, Northeastern University, Boston, MA 02155, USA;NanoLab, Electrical and Computer Engineering, Tufts University, Medford, MA 02155, USA;Center for Biomedical Engineering, Department of Medicine, Brigham and Women’s Hospital, Harvard Medical School, Boston, MA 02115, USA;

关键词: sub-threshold;    weak inversion;    analog design;    OTA;    low power;    FDSOI;   

DOI  :  10.3390/jlpea2020155

来源: mdpi

【 摘 要 】

We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.