Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Journal of Low Power Electronics and Applications

Jani Mäkipää²  Matthew J. Turnquist¹  Erkka Laulainen¹ 

[1] Department of Micro- and Nanosciences, Aalto University, FI-00076 Aalto, Finland;;VTT Technical Research Centre of Finland, FI-02044 VTT, Finland

关键词: subthreshold;    ultra-low-power;    timing-error detection;    subthreshold source-coupled logic;    SCL;    weak inversion;    dynamic supply voltage;    dynamic voltage scaling;   

DOI  :  10.3390/jlpea2020180

来源: mdpi

【 摘 要 】

This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm², and operates down to 300 mV.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.