Applied Sciences | |
Round-Off Noise of Multiplicative FIR Filters Implemented on an FPGA Platform | |
Jean-Jacques Vandenbussche2  Peter Lee1  | |
[1] School of Engineering and Digital Arts, University of Kent, Canterbury Kent CT2-7NT, UK; E-Mail:;Department ESAT, KU Leuven Kulab, Zeedijk 101 Ostend 8400, Belgium; E-Mail: | |
关键词: MFIR; FIR-filters; linear phase filters; FPGA; fixed point digital signal processing DSP; round-off noise; filter cascade structure; | |
DOI : 10.3390/app4020099 | |
来源: mdpi | |
【 摘 要 】
The paper analyzes the effects of round-off noise on Multiplicative Finite Impulse Response (MFIR) filters used to approximate the behavior of pole filters. General expressions to calculate the signal to round-off noise ratio of a cascade structure of Finite Impulse Response (FIR) filters are obtained and applied on the special case of MFIR filters. The analysis is based on fixed-point implementations, which are most common in digital signal processing algorithms implemented in Field-Programmable Gate-Array (FPGA) technology. Three well known scaling methods,
【 授权许可】
CC BY
© 2014 by the authors; licensee MDPI, Basel, Switzerland.
【 预 览 】
Files | Size | Format | View |
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RO202003190027741ZK.pdf | 1133KB | download |