A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors

Sensors

Jaeyoung Bae¹  Daeyun Kim³  Seokheon Ham³  Youngcheol Chae² 

[1] Department Semiconductor Science, Dongguk University, Seoul 100-715, Korea; E-Mail:;Department Electronic Engineering, Yonsei University, Seoul 120-749, Korea; E-Mail:;Samsung Electronics Co.Ltd, Kiheung 446-711, Korea; E-Mails:

关键词: CMOS Image Sensor (CIS);    Two-Step Single-Slope ADC;    column self-calibration;    low noise;   

DOI  :  10.3390/s140711825

来源: mdpi

【 摘 要 】

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

【 授权许可】

CC BY   
© 2014 by the authors; licensee MDPI, Basel, Switzerland.